Information display system

ABSTRACT

An information display system including display means for displaying a sequence of coordinate points, each point having an ordinate and an abscissa value. The system having means for subtracting a selectable constant from each ordinate value prior to display, and means for multiplying the difference of the subtraction before display. Pulse means are provided for selectively varying the constant to be subtracted at a selectable rate. Means are also provided for varying the multiplication factor. Also, means are provided for marking a coordinate point on the display means and for selectively using the ordinate value of the selected coordinate as the constant to be subtracted, thus centering or zeroing the displayed figures around the marked point. Finally, limit means are provided at the output of both the subtraction means and the multiplier means for providing maximum and minimum output numbers from each.

United States Patent 1191,

Schumann et al.

[ INFORMATION DISPLAY SYSTEM Jan. 22, 1974 Primary Examiner-Joseph FRuggiero Attorney, Agent, or Firm-Lew Schwartz [75] Inventors: Robert W.Schumann, Madison;

Arthur F. Smith, Verona, both of Wis. [57] ABSTRACT [73] Assignee:Nicolet Instruments, Inc., Madison, A information p y System includingisp ay wi means for displaying a sequence of coordinate points, eachpoint having an ordinate and an abscissa value. [22] F'led: 1971 Thesystem having means for subtracting a selectable [21] Appl. No.: 190,583constant from each ordinate value prior to display, and means formultiplying the difference of the subtraction before display. Pulsemeans are provided for 2% F8 g2 selectively varying the constant to besubtracted at a d 198 152 selectable rate. Means are also provided forvarying 1 0 283 D [1 f 324299 the multiplication factor. Also, means areprovided for marking a coordinate point on the display means and forselectively using the ordinate value of the selected [56] ReferencesC'ted coordinate as the constant to be subtracted, thus cen- UNITEDSTATES PATENTS tering or zeroing the displayed figures around the 3,011,164 11/1961 Gerhardt 340/324 A marked point. Finally, limit means areprovided at the 3,437,873 4/1969 gger 340/324 A output of both thesubtraction means and the multi- Kleslmg A plier means for providingmaximum and minimu 3,540,012 11/1970 Ehrman 340/324 A output numbers feach 3,637,997 1/1972 Petersen 340/324 A X 31 Claims, 13 Drawing Figures-0ATA so I A 32 MULTI- ACCUMULATING SUBTRACTION 3 35 34% COMPARATORTRANSFER 33 i 1 GATES 3 1/37 cougren 1 COUNT- DOWN COUNT-UP 2|SUBTRAHEND v E COUNTER 1 25 l 43 1- g COUNT-DOWN COUNT-UP 22 l 1 1 44-DIGITAL T0- ANALOG 1"" 47 oecoosn g l o o I l o o 26 1 a? o o l o o l wI :1 o -o DIGITAL- TO- a: 8 ANALOG DECQDER 8 49 OSCILLATOR DEPLAY .&MARK I an x Y 4-- PAIENTEB 3.787.666

sum 1 or 5 MARKED POINT TU w H INVENTORS PRIOR ART 4 gla gflfgfifg YArthur Smzth Robert W. Schuynann,

PAIENTED JAN 2 2 I974 SHEET 0F 5 I N VEN TORS Robert w Schumann, BYArthur E Smith lFw HA INFORMATION DISPLAY SYSTEM BACKGROUND OF THEINVENTION Information display systems are well-known in the art. Digitalmeasuring instruments such as signal averagers, pulse height analyzersand other instruments of the general type include a digital memory inwhich measured informationis stored. These instruments generally includea means for displaying the stored information on a device such as acathode-ray-tube screen, and the circuitry within the instrumentsprovide for a systematic presentation of ordinate and abscissa valuesfrom the memory storage for control of the cathoderay-tube beamdeflections. Thus the display comprises a plot of coordinate points, theplot representing the variable being measured. For example, in the caseof a digital signal averager, the display may provide a coordinate plotof hundreds or thousands of coordinate points which represent thevoltage-time relationship of the measured signal.

One of the problems involved with the type of display described above isthat the vertical resolution of the data often exceeds that of thedisplay means. For example, the range of data values may be from plus131,071 units to minus 131,072 units for an 18 bit instrument. Thedecoder usually cannot decode more than 12 bits and higher resolutiondecoders are both expensive and slow. The resolution of acathode-ray-tube screen is significantly less than that required in theabove example.

A well-known method used in measuring instruments for avoiding the aboveproblem is to connect a digitalto-analog decoder to the most significantor 12 bits of the ordinate value register in the instrument, and tomultiply the ordinate values by a constant, usually 2" where n is aninteger. The multiplication is in effect an arithmetic left shift." Itproduces the same effect as re-connecting the decoder to lesssignificant bits. Such known multipliers may be changed by the operatorto select whatever magnification factor he wishes. However, such asolution to the problem raises ambiguities in-the displayed materialswhen higher magnification is desired. These ambiguities cause thedisplay to become unintelligible, as will be more fully described belowwith reference to the Figures of the drawings.

The apparatus of this invention overcomes the above-described problem byproviding not only magnification through multiplication of the ordinatevalue, but by allowing the operator to select a constant to besubtracted from each ordinate value of the display, thus keeping thatportion of the display in which he is interested on the screen of thedisplay device SUMMARY OF THE INVENTION Briefly described, the apparatusof this invention ineludes a display device and means for providingabwhich is operated manually so that an observer can vary the subtrahendat a rate and in the direction he desires. Further switch means areprovided for completely inhibiting the subtrahend from entering thesubtracter. The difference following the subtraction process ispresented to a multiplier for magnification purposes. The multiplier hasa switch which enables selection by the operator of any one of aplurality of magnification or multiplication factors. The output of themultiplier is connected by means such as a digital-to-analog converterto the Y-input of a cathode-rfiy-tube beam deflection device.Preferably, both the difference value leaving the subtracter and theproduct leaving the multiplier are limited to a maximum and minimumnumber to avoid undesirable displays.

Also provided in the apparatus of this invention, are means for markinga particular coordinate point on the displayed plot of coordinatepoints, such as a beam intensifier on a-cathode-ray-tube screen. Theoperator of the apparatus may select the particular coordinate point ofinterest prior to magnification by use of the selection apparatusprovided. Then by operating a switch, either momentarily or permanently,he may enter the ordinate value for the selected coordinate point intothe counter to become the subtrahend. This will cause a centering orzeroing of the selected coordinate point, as the amountsubtracted at theselected abscissa point will be equal to the ordinate value as long asthe switch is closed, or even when the switch is opened should the inputinformation not change. Therefore, the operator can center the area ofinterest and it will stay centered despite change of the magnificationfactor.

The centering selection apparatus comprises a comparator and anothercounter adapted to receive signals from the pulse generator. The inputabscissa information is provided to the comparator and the operator mayvary the information in the counter, at a selected rate, to quickly findthe abscissa value of the coordinate point he wishes to mark. When thevalue in the counter matches that of the abscissa information beingpresented, the comparator will recognize this and provide an outputsignal to the beam intensity device, or

other marking device used on the display means. Having visually selectedthe coordinate point of interest, the operator may actuate a switch,either momentarily or permanently, whereby the output of the comparatorwill cause the ordinate information for the matched abscissa value to beentered into the subtrahend counter, to act as the subtrahend.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1A is a representation of a plotof a plurality of coordinate points, each having an ordinate and anabscissa value, of the type used with the apparatus of this invention;

FIG. 1B is a representation of a prior art magnification of the plot ofFIG. 1A;

FIG. 1C is a representation of a further prior art magnification of theplot of FIG. 18;

FIG. 2 is a representation of an off-scale prior art magnification ofthe plot of FIG. 1A;

FIG. 3 is a representation of an uncentered magnification of the plot ofFIG. 1A, using the apparatus of this invention;

FIG. 4 is another uncentered magnification of plot of FIG. IA, using theapparatus of this invention;

FIG. 5 is a representation of coordinate points, each having an abscissaand ordinate value, showing a marked coordinate point selectively markedwith the apparatus of this invention;

FIG. 6 is a magnification of the plot of FIG. 5 indicating the centeringor zeroing of the marked point, using the apparatus of this invention;

FIG. 7 is a block diagram of the information display system of theapparatus of this invention;

FIGS. 8 and 8A are logic diagrams of the subtracter apparatus of thisinvention;

FIG. 9 is a logic diagram of the multiplier or magnification apparatusof this invention; and

FIG. 10 is a logic diagram of a portion of the multiplier apparatus ofthis invention.

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS As has been stated above,a prior art method of overcoming the problems of vertical resolution ininformation display devices has comprised use of apparatus formultiplying the vertical or ordinate value by a constant, usually 2"where n is an integer. FIG. IA shows a typical display for the casewhere n is O (2"=1). Little detail is present. FIG. 1B shows the effectof shifting twice (n=2 and "=4). This result s ir 1 a better showing'ofthe details of the coordinate plot, however, there are instances wherethe operator will wish still greater detail. FIG. 1C shows the effect ofsuch an attempt to achieve greater detail, for example, where m is equalto 3. Still better detail is shown but an ambiguity has been introducedbecause the shifting or multiplying operation has resulted in the lossof one significant bit for each ordinate in two regions. The left shifteffect of the multiplicaiton has resulted in the shifting out of asignificant bit of information. It will be apparent that it is sometimesdesirable or necessary to shift as many as ten times (m=l0) to observefine detail, and often in the prior art apparatus this highmagnification produces so many ambiguities that the display isunintelligible to the operator.

This particular problem of ambiguities is overcome with one prior artmodification with the result shown in FIG. 2. For any ordinate valuewhich, after shifting, has become ambiguous, the value is changed tothat corresponding to positive or negative full scale depending onwhether the original number was positive or negative. The value changeis applied only to the numbers presented to the information displaysystem of this invention, and the original ordinate values are retainedin the instrument measuring device memory.

Though the technique resulting in the display of FIG. 2 preventsseverely confusing ambiguous displays, it is a method which has seenlittle use because the offscale values are completely obscured and it isoften these values which contain the information the operator seeks todiscover.

The apparatus of this invention enables the supression of ambiguities,but in addition, allows data modification which enables the observer toinspect any region of the data. This modification is accomplished by thesubtraction, prior to the magnification or multiplication step, of aselectable constant from each ordinate. The constant may have any valuein the range of possible ordinate values, for example, in an 18 bitsystem, the constant values may be in the range of plus 131,071 to minusl3 1,072. For example, by subtracting a positive constant from everyordinate value of the plot of FIG. 2, the result will be the uncenteredinformation shown in FIG. 3 enabling the operator to view theinformation at the positive peak of the plot. By use of a negativeconstant, applied to the plot of FIG. 2, the uncentered plot as shown inFIG. 4 will result, enabling the operator to view the information at thenegative peak.

It is therefore apparent that utilizing the apparatus of this invention,despite the degree of magnification, it is possible to observe anydesired data region on the plot without presenting the observer withconfusing ambiguities.

The apparatus of this invention also includes apparatus for theautomatic centering or zeroing of the displayed information. Theapparatus allows the operator to select a desired coordinate point onthe plot. The ordinate value of this point then becomes the subtractionconstant and the subtraction results in the entire set of data beingmoved up or down an amount sufficient to cause the selective point to beat the center or zero level, because the amount subtracted is exactlyequal to the ordinate of the selected coordinate. Referring, forexample, to the display of FIG. 3, one can see that this plot would haveto be manually centered by the operator if a higher magnification thanthat shown were used. This manual operation can be eliminated by theapparatus of this invention. In FIG. 5, a brightened point is shown onthe plot which indicates to the operator what coordinate point he hasselected. Apparatus is provided in this invention enabling the operatorto move the brightened point along the plot until he reaches acoordinate point in a region of interest. Thereafter, the effect of theautomatic centering or zeroing feature is to keep the selected point onthe center or zero line, as shown in FIG. 6 which is a magnifiedrepresentation of the plot of FIG. 5. As will be more fully describedbelow, the automatic centering apparatus is extremely useful if the dataare changing, as is the case in many digital measuring instruments,where despite data changes the region of interest remains centered. Thisfeature is also useful for keeping a region of interest centeredregardless of what magnification is used.

Referring now to FIG. 7, there is shown a block diagram including theinformation display system of this invention. The system includes a dataaccumulating computer I, subtraction circuitry 2, multiplicationcircuitry 3, comparator 4, transfer gates 5, counter 6, subtrahendcounter 7, digital-to-analog decoders 8 and 9,

display means 10 and oscillator 11 all shown in block diagram 4.Computer 1 has an ordinate cable 30 connected to the input ofsubtraction circuitry 2 and to a set of input gates on subtrahendcounter 7. Subtraction circuitry 2 has its output connected by a cable32 to multiplication circuitry 3. The output of multiplication circuitry3 is connected through cable 33 to decoder 9,

and the output of decoder 9 is connected to a vertical deflectionvoltage input terminal on display 10, which in this preferred embodimentis an analog display means such as a cathode-ray-tube beam deflectionapparatus. Data accumulating computer 1 has an abscissa output connectedthrough a cable 35 to decoder 8 which has an output in turn connected tothe horizontal deflection voltage on display means 10. Cable 35 is alsoconnected to the input of comparator 4. Comparator 4 has another inputconnected to the output of counter 6 by a cable 37. The output ofcomparator 4 is connected by a line 42 to a marking device on displaymeans 10, such as a beam intensifier input. Line 42 is also connected toa pair of terminals 21 and 22 of a switch 20. The wiper arm of switch 20is connected by a line 43 to the gates on subtrahend counter 7. Theoutput of counter 7 is connected through cable 38 to the input oftransfer gates 5. The output of transfer gates 5 is connected through acable 34 to the input of subtraction circuitry 2. A switch 24 isconnected between gates 5 and circuitry 2 for selective enabling ofgates S. The output of subtraction circuitry 2 is connected by a cable32 to multiplication circuitry 3. A multiplication factor selectionswitch 25 has a plurality of terminals connected to multiplicationcircuitry 3. A multiplication factor selection switch 25 has a pluralityof terminals connected to multiplication circuitry 3 for selection of amultiplication factor. Oscillator 11 has a pair of outputs 48 and 49each carrying pulses at different frequencies. Lines 48 and 49 areconnected to terminals on a switch 26 and a switch 27. Switch 26 has a Afirst wiper arm connected through a line 44 to a countup input terminalon counter 6 and a second wiper arm connected by line 45 to a countdowninput terminal on counter 6. Switch 27 has a first wiper arm connectedby line 46 to a count-up input terminal on counter 7 and a second wiperarm connected by a line 47 to a count-down input terminal on counter 7.

To best understand the operation of the apparatus shown in block diagramin FIG. 7, it will be of value to first discuss the operation in generalterms. For the operation of this preferred embodiment, it is assumedthat display means is of the type having a cathode ray-tube and that,therefore, the digital or binary form of information must be transferredto the form of analog voltages for beam deflection purposes. Thisnecessitates digital-to-analog decoders 8 and 9, which would not benecessary in other embodiments of the invention which may use otherdisplay media such as a matrix array of light emmitting elements whichcan operate directly from digital signals. However, the same problems indevice or human eye resolution would exist for other types of displaymedia as exist for the cathoderay-tube, and the same kind of alterationson the number value presented to the device would apply as are neededfor the numbers presented to the digital-toanalog converters in thispreferred embodiment of the invention.

It is also assumed that the resolution of the digital-toanalogconverters 8 and 9 is 12 bits. This choice is made for the preferredembodiment because this is a practical resolution limit for a low costfast converter. It will apparent that the same principles present in thepreferred embodiment of the apparatus of this invention would apply ifthe converter had loweror higher resolution.

As more fully discussed above, because of the imperfect resolution ofthe digital-to-analog decoders and other display medium and the humaneye, significant detail is not always visible on the screen, and thevertical scale of the display must at times be magnified. If there weresufficient resolution in the instruments, it would be sufficient toamplify the digital-to-analog converter output voltage and add a voltagebias to that amplified signal in such a manner that the region ofinterest is displayed on the screen in adequate detail. This solution isnot normally acceptable because such amplification also magnifiesinstability in the digital-toanalog converter, thereby causing thedisplayed information to jitter or wander on the screen. Further, thereis a tendency for the displayed points to be fuzzy due to higherfrequency noise and crosstalk. Also, it will be apparent that such asolution would not be applicable to display devices directly controlledby digital information which would not utilize digital-to-analogdecoders.

For the purposes of this description a particular ordinate value of acoordinate point may be represented as a twos complement number:

where the coefficient 17 may have the value 0 or l, and the othercoefficients k,- may have the values 0 or 1. In all digital circuits thecoefficient for all bits will be 0 or 1, with the negative sign impliedfor the left bit. This is conventional twos complement representation.The digital-to-analog decoder treats a l in the 17th bit position as anegative coefficient.

A conventional notation for a twos complement binary number 1,- is aseries of ones and zeros representing, in order the coefficients of theterms. An example Y=111 1110001000001 10 which is a negative numberequal to the decimal number 3834.

In the embodiment of the apparatus of this invention, an accurateconversion to analog voltage form cannot be made of an 18 bit number,for the digital-to-analog converter has only 12 bits of resolution. Agood representation can be obtained by connecting the digital-toanalogconverter to the most significant 12 bits, in effect thereby roundingoff the numbers to 12 bits. The voltage output would, for the abovenumber, then be proportional to 3840 rather than 3834, because the lower6 bits would be ignored. Any number Y,- in the range111111000100000000to111111000100111111 would produce the same voltageoutput from the digi- ,tal-to-analog converter. No matter whatamplification may be used to operate on the output of thedigital-toanalog converter to increase the vertical magnification of thedisplay, there would be no regaining of rounded off and therefore lostinformation as the least significant bits of all applied numbers areignored.

Multiplication, by a left shift by a number in a register (except thesign bit) makes the digital-to-analog converter responsive to the lowerorder bits, but may result in the shifting-out of a significant bit, andambiguities such as in FIG. 1C will result. By shifting-out" is meantthe appearance of a significant bit to the left of the 12 bits to whichthe converter is connected. 1n the case of negative numbers, the first 0and all lower bits are significant. For positive numbers the first l andall lower bits are significant.

It is one function of the apparatus shown in FIG. 7 to modify thenumbers prior to multiplication, to avoid ambiguities in the region ofinterest. This is achieved by subtracting a constant of sufficientmagnitude and proper sign from the original ordinate values, such thatthe multiplication operation will not cause the number to exceed 17significant bits plus the sign bit. This same constant is subtractedfrom all ordinates.

It will be understood that the ordinate values received from computer 1are not necessarily of predictable values and that even if they shouldbe, subtraction of a constant from some numbers may prevent ambiguitiesdue to overflows in multiplication but may well cause ambiguities withregard to other numbers. However, though initially the numbers areunpredictable, it is helpful that the appearance of the coordinate plotgives the observer an immediate indication of their general magnitudes.As will be seen, the human operator may use his judgment to decide whatmagnification may be needed to reveal fine detail of the plot, and willbe aware that to avoid ambiguity in some region of immediate interest,he must add or subtract a small or large constant from all ordinates.

FIG. 2 shows a common situation where ambiguities have occurred near thetop and bottom of the features of the coordinate plot. If the operatordesires to observe the top, a positive constant should be subtractedfrom all ordinates prior to multiplication. The result of such anoperation is shown in FIG. 3. The magnitude of the constant is notcritical, as the operator may experimentally increase or decrease theconstant value until the region he wishes to observe is unambiguous. Inthe case of FIG. 3,- the operator has chosen a constant which hasaggravated the overflow problem in some regions of the waveform, but asthe operator wished to see that portion of the positive peak which isshown on scale in FIG. 3, he need not be concerned about the aggravatedportion, further, he may later decrease the constant in value until thedisplay of FIG. 4 is achieved, if he is interested in observing the morenegative regions of the same plot. Referring again to FIG. 7 in moreparticularity, data accumulating computer 1 may be any one of a widevariety of existing devices. To best understand the preferred embodimentit is assumed that computer 1 provides 18 bit twos complement ordinatevalues and 12 bit abscissa numbers in sequence, repeatedly, with theabscissa and ordinates of each coordinate provided simultaneously. Thebit length of the ordinates, and the number of coordinates involved, maybe different for different computers but the same principles will apply.It .is assumed that the coordinate points are provided systematically,for example, one at a time in sequence of increasing abscissa values,and that cable 30'represents 18 wires and cable 35 represents 12 wires.A reasonable sequence of presentation involves periodic presentation ofcoordinates at intervals of nominally microseconds, with the sequencerepeated as often as the operator wishes to observe the information. Itmay be desirable to include buffer registers to hold the coordinatevalues duringeach 10 microsecond interval to free the computer for othertasks during those times. It will also be apparent that it is notmandatory that the coordinates be presented in order of increasingabscissa values but it is preferable that each coordinate be presentedapproximately as often and for as long as each other coordinate.

Subtraction circuitry 2 subtracts from the ordinate values presentedthrough cable 30 a constant subtrahend contained in subtrahend counter7. The constant is passed through gates 5 whenever switch 24 is in theenable position and then through cable 34 to circuitry 2. As will bemore fully described below, subtraction circuitry 2 has the property ofproviding 18 bit twos complement output numbers on cable 32, whichnumbers or differences in general equal the difference between theordinate value Y, and the subtrahend, except that a provision is made incircuitry 2 so that if the difference exceeds plus 2 -1 or falls below-2 the output S,-' resulting is made to equal 2"l or 2", respectively.

Multiplier 3 receives the difference S,- throug h cable 32 and alsoreceives a signal on one of the output wires of multiplication factorselector switch 25. The output product of multiplication circuitry 3 islimited to 12 bits in this preferred embodiment. The 12 bits do notexceed the least significant bits of the product, and include only thenext eleven bits and the sign bit of the product. Any product whichexceeds 2"1 or' falls below 2 is replaced with one of those respectivevalues, thereby producing 12 bit output numbers 2] or .2ll

It is preferred that subtraction circuitry 2 and multiplication circuit3, be static devices for continually providing the difference andproduct values described above, except for momentary settling delaysfollowing changes in the ordinate or the subtrahend. Therefore, nosynchronization is needed between the computer and other components.

The modified product from circuitry 3 passes through cable 33 to decoder9. Decoder 9 operates in a manner well known to those skilled in the artto provide analog voltages which are proportional to the input digitalinformation on cable 33. The output voltages of decoder 9 are ofsufficient magnitude to produce a full scale vertical beam deflection ondisplay means 10 if the modified product from circuitry 3 is 2"-l or-2". The horizontal deflection of display apparatus 10 is controlled bythe voltage from digital-toanalog decoder 8, which receives abscissavalues from computer 1 through cable 36.

As stated above, the subtrahend is transmitted from counter 7 throughgates 5 and cables 38 and 34. When switch 21 is in the enable position,the gates are enabled and the state of counter 7 is transmitted tocircuitry 2. When switch 21 is in the downward position, gates 5 areblocked and a zero is presented through cables 34 to subtractioncircuitry 2. The design of transfer gates 5 are well-known to thoseskilled in the arts.

Subtrahend counter 7 is preferably an up-down counter, also well-knownto those skilled in the art, which has a count-up input terminal and acount-down input terminal. The state of counter 7 may be altered upwardsone count for each pulse supplied on wire 46 to the count-up inputterminal, and downwards one count for each pulse supplied on wire 47 tothe countdown input terminal. Subtrahend counter 7 also has a gatedparallel input such that a pulse on wire 43 enables input gates toinsert into the counter the value Y, representing the instantaneousordinate value present on cable 30.

Oscillator or pulse generator 11 continually provides pulses on lines 48and 49. The pulses on wire 48 are of a higher frequency, for example,about 400 Hertz and pulses on wire 49 are of a lower frequency, forexample, about 10 Hertz. Switch 27 controls the application of pulses tothe count-up input and count-down input of counter 7. When the switch 27is in its center position, as shown in FIG. 7, no pulses are transmittedto counter 7. When switch 27 is moved one position up or one positiondown, pulses are transmitted respectively, through wire 47 to thecount-down input of counter 7 and through wire 46 to the count-up inputof counter 7. Note that an upward position of switch 27 causes the stateof subtrahend counter 7 to decrease. This is a preferred condition asdecreasing the counter state will cause an increase in the remainder ordifference output of subtraction circuitry 2, and thus cause thedisplayed data to move upwards, the same direction the switch is moved.Similarly, a downward movement of switch 27 causes the displayed data tomove downward on the screen of display device 10. When switch 27 isoperated to the second position either upwards or downwards, the stateof the counter will change at a higher frequency. It is apparent thatthe choice of frequencies is completely arbitrary and it is as apparentthat more than two frequencies can be provided from one or moreoscillators such as 11, and that each of the pluralities of frequenciescan be applied to counter 7.

In FIG. 7, the apparatus including comparator 4, counter 6, and switches20 and 26 will act as a means for automatically centering or zeroing thedata for the operator. Counter 6 is preferably an up-down counter havinga count-up input terminal and a count-down input terminal. Switch 26operates in the manner described above with regard to switch 27, butoperates independently of switch 27. Thus, the operator may, byactuating switch 26 provide pulses from oscillator 11, of either of theselected frequencies, to either the count-up input terminal or thecount-down input terminal of counter 6 through, respectively lines 44and 45. Comparator 4 is a digital comparator of a type wellknown in theart. It is continually comparing the abscissa value present on cable 35with the counter state present on cable 37. When a comparison oragreement exists, a signal in the form of a selected voltage will appearon wire 42. Wire 42 is connected to the marker input of display device10, in this preferred embodiment a beam intensifier circuit, whichcauses a brightening of a displayed coordinate point having theabscissavalue. stored in counter 6. Thus, the operatormay move the intensifiedbeam along the coordinate plot, at various speeds, and in twodirections, simply by moving switch 26 upward or downward as desired.Switch 26 is preferably a spring-loaded return-to-center switch, as isswitch 27. Therefore, when the operator has moved the marker orintensified beam to a coordinate point in a region of interest, he maysimply release switch 26 and the intensified beam or marker will stay atthe selected point.

Switch 20 is also a spring-loaded return-to-center switch in oneposition and is a permanent connection switch in the other position.That is, when the wiper arm of switch 20 is moved to terminal 21, amomentary contact will be made which will be broken when the operatorreleases the wiper arm. When the wiper arm of switch 20 is moved intocontact with lower terminal 22, it will remain in that position evenwhen the operator releases the switch. When the wiper arm of switch 20is in contact with either of terminals 21 or 22, a signal on line 42will be transmitted through line 43 to enable the gates at the input ofsubtrahend counter 7. The ordinate value y,, then present on cable 30will then pass through the gates of counter 7 to change the state ofcounter 7. Therefore, that ordinate value, Y will be subtracted from allfurther ordinate values. The ordinate value thus entered into subtrahendcounter 7 is that which corresponds to the coordinate whose abscissavalue equals the state of counter 6. Therefore, the data displayed ondisplay device will be vertically centered, that is zeroed, as long asline 43 is connected through switch to terminal 21 or 22. The displaywill remain centered thereafter even if switch'20 is open, unless theordinate values provided by computer 1 are changing for some reason, orunless updown counter 7 is changed by adding pulses with switch 27, orunless gates 5 are disabled through the use of switch 24.

It is apparent that up-down counter 6, as up-down counter 7, could besome other storage means as long as it is variable to enable theoperator to select a coordinate point of interest for automaticcentering.

Reference is now made to FIGS. 8 and 8A which are logic schematics ofsubtraction circuitry 2. There is shown a binary adder of a type anddesign well known to those skilled in the art. Cable 30 carryingordinate values Y,- is shown as having 18 lines, 200-217 connected toadder 100. Lines 200-217 each carry the indicated bit value of Y YY"ranging from the least significant bit of the ordinate value to the mostsignificant bit. Cable 34 is shown as comprising seventeen lines,500-517 carrying, respectively, the subtrahend bit values C -C Each oflines 500-517 is connected to one of a plurality of inverters 101. Theoutput of inverters 101 are connected to binary adder 100. A carry pulseis presented to binary adder 100 through line 113. The output of binaryadder 100 is presented on a plurality of lines 800-817. Each of lines800-817 is connected to one input of a plurality of two-input AND gates102. Each output of AND gates 102 is connected to one input of aplurality of two-input OR gates 112.

Also in FIGS. 8 and 8A are shown a pair of threeinput AND gates 103 and105, and another two-input AND gate 100. Line 217, representing the mostsignificant bit y of the ordinate value presented on cable 30, isconnected to a first input of gate 105 and through an inverter 106 to afirst input of gate 103. Line 517, representing the most significant bitC of the subtrahend value presented on cable 34, is connected to asecond input on gate 103 and is connected through its inverter 101 to asecond input on gate 105. Output line 817 of binary adder 100,representing the most significant of the difference value is connectedto the third input on gate 103 and is connected through an inverter 104to the third input on gate 105. The output of gate 103 is connectedthrough a line 902 to all of the second inputs of OR gates 112 exceptthat OR gate representing the most significant bit of the resultingoutput from the subtraction circuitry. The output of gate 103 is alsoconnected through an inverter 108 to a first input on gate 110. Theoutput of gate 105 is connected to the second input of the OR gate 112representing the most significant bit of the result from subtractorcircuitry 2, and is also connected through an inverter 109' to thesecond input of gate 110. The output of gate 110 is connected through aline 904 to the second input on each of AND gates 102. The outputs of ORgates 112 are connected to a plurality of lines 300-317 representing thevalue of the final difference from subtraction circuitry 2, S-S".

The subtraction operation of circuitry 2 is accomplished by invertingeach bit of the subtrahend C by means of inverters 101, applying a carryinto adder 100 through wire 113, and applying to adder 100 the ordinatevalue on cable 30 through wires 200-217. The subtraction method ofinverting the bits of the subtrahend C and including a carry input iswell-known to those skilled in the art and will produce the differencevalue, in this case y,- C.

In this preferred embodiment of the invention ambiguities in the displayon device 10 are avoided by preventing or limiting the difference valueof circuitry 2 and the product value from multiplication circuitry 3from exceeding maximum and minimum limits, in this preferred embodiment2"1 or 2". Gates 102, 103, 105, 110, and 112 serve the purpose ofmodifying the output numbers on wires 300-317 whenever either limit hasbeen exceeded. It will be apparent that whenever the ordinate value andthe subtrahend are of unlike sign, it is possible that there will be adifference in excess of the chosen limits. If y is positive anc Cnegative, a positive overflow may occur, which will be indicated by anegative sign on wire 817, the most significant bit of adder 100.Obviously, the difference value should be positive in this case, so thata negative result will indicate a positive overflow. And gate 103 willprovide a positive output ifC" is a l (negative sign), y

. is a (positive sign) and the most significant adder output bit on line817 is a 1 (negative sign). Inverter 106 inverts the signal on line 217,which was bit y so that all three inputs of gates 103 will be positiveif y is a 0 (positive sign). Whenever the output of gate 103 on wire 102is positive, all but one of OR gates 112 are enabled to provide 1outputs on lines 300-316 representing difference values S-S. Also,inverter 108 will then produce a 0 at gate 110, which therefore causes a0 on wire 904 to AND gates 102 insuring that there is a 0 input to ORgate 112 representing the. most significant bit of the output ofsubtraction circuitry 2. Thus, the sign bit of the modified differenceon line 317 is forced to be a 0" (positive sign) as OR gate 112 cannotbe receiving a 1 from the output AND gate 105. Therefore, the modifiednumber, 5,,

representing the output from subtraction circuitry 2 will be equal to 21.

The output of gate 105 will be positive ifC is positive, Y, is negativeand the most significant bit from the adder appearing on line 817 is a0, as such a condition can only exist if there was a negative overflow.The output 1 from gate 105 will force OR gate 112, representing the mostsignificant bit of the subtraction circuitry 2 output, to produce a 1 onwire 317 (negative sign). All other output bits from gates 112representing numbers S toS, are forced to be 0 because all of AND gates102 are disabled by the output of gate 110 on wire 904, as the 1 outputof gate 105 is inverted by inverter 109 to appear as a 0" at the inputof gate 110. Therefore the output number of circuitry 2, 5,, is forcedto be equal to 2 in this case.

In FIGS. 8 and 8A, the'output on line 317 is shown as representing notonly S but also S, S, S, S and 8. As will be apparent, this is aconvenience in representation only. As will be more fully described inthe discussion below of FIG. 9, multiplication circuitry 3 requires thatthe input multiplicand have 23 bits The two's complement S, has the samemeaning if the sign bit and the first significant bit of the number areinterposed with as many bits as desired, each having the samecoefficient as the sign bit. For example, 111001 is of the same value asl 11 1 1001 in twos complement representation, and 000001 1 has the amevalue as 00000011. The subtraction circuit 2 output numbers are 23 bitnumbers in twos complement form that have a range of possible valuesfrom 2"-1 to 2"'.

Referring now to FIG. 9, there is shown a multiplier '150 of aconventional design well-known to those skilled in the art. Multiplierhas inputs connected to lines 300-317 representing the bits of theoutput of subtraction circuitry remainder, S Multiplier 150 also hasa'plurality of inputs on lines 142 148 representing, respectively,multiplication factors of 64, 32, 16, 8, 4, 2, and 1. Each of lines 142148 is connected to a separate terminal on multiplication factorselection switch 25, and each of lines 142 148 is connected through aresistor 158 to ground. The wiper arm of switch 25 is connected to apositive voltage.

Multiplier 150 has a plurality of output lines 125-141 representing thevalue of the product output PP Lines 125-135 are connected to a modifier151. Lines 136-141 are connected to the inputs of a six input OR gate162 and are connected through a plurality of inverters to anothersix-input OR gate 156. The output of OR gate 152 is connected to oneinput of a twoinput AND gate 153 which has an output connected by a line159 to modifier 151. The output of gate 156 is connected to one input ofa two-input AND gate 157 which has an output connected by a line tomodifier 151. Line 317, representing bits S"S, is connected through aninverter 154 to the second input of AND gate 153. Line 317 is alsoconnected directly to the second input of AND gate 157. Modifier 151 hasa plurality of output lines 400-410. Another output line 411 isconnected to line 317. Lines 400-411 represent cable 33 of FIG. 7.

The operation of the apparatus of FIG. 9 will now be discussed.Multiplier 150 is a conventional binary multiplier that responds to theinput multiplicand (without sign) on wires 300-316, and the multipliersignal represented by the positive voltage on one of wires 142-148, in amanner to shift the bit positions 6, 5, 4, 3, 2, 1 or 0 positions to theleft depending on whether the multiplier is 64, 32, 16, 8, 4, 2 or 1. Asthere are seventeen multiplicand bits, there may be as many as 23product bits produced. All but the least significant six of theseproduct bits appear on wires [25-141 as product bits P through P.

Bits P through P will pass through modifier 151 to provide the 11 leastsignificant bits applied to digitalto-analog converter 9 in FIG. 7, andthe sign bit S" is always' transmitted to converter 9, unchanged.However, if the multiplication operation has caused any of bits P"-l tobe significant, that is to be l if the sign bit S" is a 0, or to be 0 ifthe sign bit is a "1, then modifier circuit 151 causes all of the bitsrepresented by lines 400-410 to be 1 if the sign bit is a 0, or causesthem all to be 0 if the sign bit is a l Such a significant bit among thebits P indicates a multiplication overflow, and modifier 151 causes thenumber presented to converter 9 to be either 2" 1 or -2" according tothe direction ofoverflow. Gate 152 in combination with converter 154 andgate 153 provides an indication of positive overflow on wire 159.Inverters 155, in combination with gate 156 and gate 157 provide anindication of positive overflow on wire 159. Inverters 155, incombination with gate 156 and gate 157 provide an indication of negativeoverflow on wire 160. The design of modifier circuit 151 is that of asimple logic circuit. A particular output bit for appearance on any ofline 400-410 is caused to be equal to P" if neither wire 159 nor 160 ispositive. If wire 159 is positive, the particular output bit is causedto be posicaused to be negative.

Referring now to FIG. 10, there is shown the output logic used inmultiplier 150 to achieve generation of an output bit P". For eachoutput P there is provided an OR gate 123 having seven inputs. Alsoprovided are seven two-input AND gates 116122, each of which has anoutput connected to an input on gate 123. Gate 116 has one of its inputsconnected to the input line representing the input S" for which theoutput product P" is desired. Gate 117 has one of its inputs connectedto the line representing 8". Gate 119 has one of its inputs connected tothe line representing 8. Gate 120 has one of its inputs connected to theline representing 8". Gate 121 has one of its inputs connected to theline representing 8". Gate 122 has one of its inputs connected to theline representing S" To achieve selective multiplication, each of gates116-122 is connected to a different of lines 142-148, which are enabledby selector switch 25. Thus, gate 116 has its other input connected toline 148, gate- 117 has its other input connected to line 147, gate 118has its other input connected to line 146, gate 119 has its other inputconnected to line 145, gate 120 has its other input connected to line144, gate 121 has its other input connected to line 143 and gate 122 hasits other input connected to line 142.

If select switch 25 is set for a times 1 multiplication then, forexample, gate 116 will be enabled and S" will be passed directly throughgate 123 to become P". If, on the oher hand, selector switch 25 is setfor a times 32 multiplication, then only gate 121 will be enabled and 8"will be passed through gate 123 to become P" in the example, thusachieving a five place left shift.

The apparatus of this invention as described above can be utilized informs other than the preferred embodiment without departing from thespirit and scope of this invention. For example, the abscissa values mayrepresent an angle, in a polar plot of information, rather than therectilinear plot described. The selected coordinate can be marked bymeans other than intensifying the displayed point. It will also beapparent to those skilled in the art that use of addition of constantsrather than substration is essentially the same process, addition simplybeing a negative subtraction. Further, it will be recognized by thoseskilled in the artthat factors of multiplication can be selected fromany reasonable constants rather than just integer powers of two. Also,the addition or subtraction process, and the multiplication process, maybe carried out, for example, with an instrument computer rather than bythe external hardware as described in the preferred embodiment. Overflowsensing and ordinate value modification may also be carried out, forexample, by a computer rather than with the hardware described. Thereare other obvious variations in apparatus which may be used toaccomplish the objective of vertical scale expansion without ambiguousdisplay.

What is claimed is:

1. In digital instrument apparatus including instrument means forproviding sets of binary numbers representative of coordinate points,and means for displaying the coordinate points connected to theinstrument means, the improvement comprising: means connected to theinstrument means, for subtracting a selectable constant binary numberfrom one binary number of each coordinate set; and means connectedintermediate the means for subtracting and the display means,

for multiplying the difference of the one binary number by a selectablebinary number. 7

2. The apparatus of claim 1 in which the means for subtracting includes:binary counter means having input means; and pulse means connected tothe binary counter input means,'for varying the constant binary number.

3. The apparatus of claim 2 in which: the binary counter comprises anup-down counter; and the binary counter input means includes count-upinput means and count-down input means.

4. The apparatus of claim 3 in which the pulse means comprises: pulsegenerator means having output means; switch means; the switch meansconnected to the pulse generator output means, the count-up input meansand the count-down input means; and the switch means operable to a firstposition disconnecting the pulse generator output means from the binarycounter input means, a second position connecting the pulse generatoroutput means to the count-up input means and a third position connectingthe pulse generator output means to the count-down input means.

5. The apparatus of claim 4 in which the switch means includes: levermeans manually operable to select each of the first, second and thirdpositions; and means connected to the lever mean for normally biasingthe lever means to the first position.

6. The apparatus of claim 4 in which: the pulse generator means includesmeans for providing pulses at a plurality of frequencies; and saidswitch means is operable to select any one of the frequencies when in hesecond or third position.

7. The apparatus of claim 2 including: gate means connected intermediatethe binary counter means and the means fon subtracting; and gate switchmeans connected to the gate means for selectively opening and closingthe gate means.

8. The apparatus of claim 2 including: further binary counter means;means connecting the further binary counter means to the pulse means forvarying the count stored therein; comparator means; means connecting thecomparator means to the instrument means, for providing thereto anotherbinarynumber of each coordinate set; means connecting the comparatormeans to the further counter means; signal output means on thecomparator means for providing an output signal only on comparisonbetween the other binary number in the comparator means and the count inthe further counter means; gate means connecting the instrument means tothe binary counter input means for providing the one binary number tothe binary counter means;.switch means connecting the signal outputmeans to the gate means, the switch means having on and off positions;and the gate means responsive to the signal from the signal output meanswhen the switch is in the on position, for enering the one binary numberin the binary counter means.

9. The apparatus of claim 8 including: marking means in the displaymeans for marking a selected coordinate point; and means connecting themarking means to the signal output means.

10. The apparatus of claim 1 in which the means for subtractingincludes: limit means for establishing a maximum difference of the onebinary number and a minimum difference of the one binary number.

11. The apparatus of claim 1 in which the means for multiplyingincludes: limit means for establishing a maximum product of thedifference of the one binary number times the selected binary number anda minimum product of the difference of the one binary number times theselected binary number.

12. The apparatus of claim 8 in which: the further binary counter meanscomprises an up-down counter; and the further binary counter meansincludes input means comprising count-up input mean and countdown inputmeans.

13. The apparatus of claim 12 in which the pulse means comprises: pulsegenerator means having output means; switch means; the switch meansconnected to the pulse generator output means, the count-up input meansand the count-down input means; and the switch means operable to a firstposition disconnecting the pulse generator output means from the binarycounter input means, a second position connecting the pulse generatoroutput means to the count-up input means and a third position connectinghe pulse generator out put means to the count-down input means.

14. The apparatus of claim 13 in which the switch means includes: levermeans manually operable to select each of the first, second and thirdpositions; and means connected to the lever means for normally biasingthe lever means to the first position.

15. The apparatus of claim 12 in which: the pulse generator meansincludes means for providing pulses at a plurality of frequencies; andsaid switch means is operable to select any one of the frequencies whenin the second or third position.

16. In an information display system in which sets of coordinate pointsare sequentially displayed on display means, each of the coordinatepoints having an ordinate value and an abscissa value, the improvementcomprising: abscissa input means for receiving digital signalsrepresentative of the abscissa value of each coordinate point; ordinateinput means for receiving digital signals representaive of the ordinatevalue of each coordinate point; subtraction means having minuend inputmeans, subtrahend input means anddifference output means; digitalstorage means having input means and output means; multiplication meanshaving multiplicand input means, multiplier input means and productoutput means; means connecting the abscissa input means to the displaymeans; means connecting the ordinate input means to the minuend inputmeans; means connecting the digital storage means output means to thesubtrahend input means; means connected to the digital storage meansinput means, for selectively supplying digital signals thereto forstorage; means connecting the difference output means to themultiplicand input means; means connected to the multiplier input meansfor selectively supplying signals thereto for varying the multipliervalue; and means connecting the product output means to the displaymeans.

17. The system of claim 16 in which the means connecting the digitalstorage means output means to the subtrahend input means includes:inhibit means for selectivley inhibiting transfer of information fromthe digital storage means to the subtrahend input means.

18. The system of claim 17 in which the inhibit means includes: gatemeans connected intermediate the digital storage means output means andthe subtrahend input means; and switch means connected to the gate meansfor selectively enabling the gate means.

19. The system of claim 16 in which: the digital storage means comprisesdigital up-down counter means; and the digital storage means input meansincludes count-up input means and count-down input means.

20. The system of claim 19 in which: the means for supplying digitalsignals comprises pulse generator means haing output means; and switchmeans connected intermediate the generator output means and the count-upand count-down input means.

21. The system of claim 20 in which: the generator means includes meansfor generating pulses at different rates; and the switch means ismovable to connect a selected rate to the selected one of the count-upand count-down input means.

22. The system of claim 16 in which the difference output meansincludes: difference limit means for inhibiting transfer of any numberto the multiplier means when the number is greater than a firstpredetermined value or less than a second predetermined value.

23. The system of claim 16 in which the product output means includes;product limit means for inhibiting transfer of any number to thedisplaymeans when the number is greater than a first predetermined value orless than a second predetermined value.

24. The system of claim 16 including: means for entering the ordinatevalue corresponding to the selected abscissa value of any selectedcoordinate point into the digital storage means; and means connectingthe means for storing to the abscissa input means, the ordinate inputmeans and the digital storage input means.

25. The system of claim 24 including: mark means on the display means;and means connecting the means for entering to the mark means, formarking a selected coordinate point on the display means.

26. The system of claim 19 including: gated input means on the up-downcounter means; furher counter means having input and output means;comparator means having input and output means; means connecting theordinate input means to the gated input means;

control means connecting the comparator output means to the gated inputmeans; means connecting the abscissa input means to the comparator inputmeans; means connecting the further counter means output means to thecomparator input means; and means connecting the further counter inputmeans to the means for supplying digital signals.

27. The system of claim 26 including: mark means on the display meansfor marking a selected displayed coordinate point; and the control meansconnected intermediate the mark means and the comparator output means.

28. The system of claim 27 in combination with the system of claim 20 inwhich: the further counter means comprises a further up-downcountermeans having further count-up input means and further count-down inputmeans; and further switch means connected intermediate the generatoroutput means and the further count-up and further count-down inputmeans.

29. The system of claim 28 in combination wih the system of claim 21 inwhich: the furher switch means is movable to connect a selected rate tothe selected one of the further count-up and further count-down inputmeans.

30. In apparatus for displaying coordinate points on display means, eachcoordinate point having at least an abscissa value and an ordinatevalue, the improvement comprising: abscissa input means; ordinate input18 connecting the subtraction means between the ordinate means and thedisplay means comprises: multiplication means for multiplying a receivedvalue by a selectable factor.

1. In digital instrument apparatus including instrument means forproviding sets of binary numbers representative of coordinate points,and means for displaying the coordinate points connected to theinstrument means, the improvement comprising: means connected to theinstrument means, for subtracting a selectable constant binary numberfrom one binary number of each coordinate set; and means connectedintermediate the means for subtracting and the display means, formultiplying the difference of the one binary number by a selectablebinary number.
 2. The apparatus of claim 1 in which the means forsubtracting includes: binary counter means having input means; and pulsemeans connected to the binary counter input means, for varying theconstant binary number.
 3. The apparatus of claim 2 in which: the binarycounter comprises an up-down counter; and the binary counter input meansincludes count-up input means and count-down input means.
 4. Theapparatus of claim 3 in which the pulse means comprises: pulse generatormeans having output means; switch means; the switch means connected tothe pulse generator output means, the count-up input means and thecount-down input means; and the switch means operable to a firstposition disconnecting the pulse generator output means from the binarycounter input means, a second position connecting the pulse generatoroutput means to the count-up input means and a third position connectingthe pulse generator output means to the count-down input means.
 5. Theapparatus of claim 4 in which the switch means includes: lever meansmanually operable to select each of the first, second and thirdpositions; and means connected to the lever mean for normally biasingthe lever means to the first position.
 6. The apparatus of claim 4 inwhich: the pulse generator means includes means for providing pulses ata plurality of frequencies; and said switch means is operable to selectany one of the frequencies when in he second or third position.
 7. Theapparatus of claim 2 including: gate means connected intermediate thebinary counter means and the means for subtracting; and gate switchmeans connected to the gate means for selectively opening and closingthe gate means.
 8. The apparatus of claim 2 including: further binarycounter means; means connecting the further binary counter means to thepulse means for varying the count stored therein; comparator means;means connecting the comparator means to the instrument means, forproviding thereto another binary number of each coordinate set; meansconnecting the comparator means to the further counter means; signaloutput means on the comparator means for providing an output signal onlyon comparison between the other binary number in the comparator meansand the count in the further counter means; gate means connecting theinstrument means to the binary counter input means for providing the onebinary number to the binary counter means; switch means connecting thesignal output means to the gate means, the switch means having on andoff positions; and the gate means responsive to the signal from thesignal output means when the switch is in the on position, for eneringthe one binary number in the binary counter means.
 9. The apparatus ofclaim 8 including: marking means in the display means for marking aselected coordinate point; and means connecting the marking means to thesignal output means.
 10. The apparatus of claim 1 in which the means forsubtracting includes: limit means for establishing a maximum differenceof the one binary number and a minimum difference of the one binarynumber.
 11. The apparatus of claim 1 in which the means fOr multiplyingincludes: limit means for establishing a maximum product of thedifference of the one binary number times the selected binary number anda minimum product of the difference of the one binary number times theselected binary number.
 12. The apparatus of claim 8 in which: thefurther binary counter means comprises an up-down counter; and thefurther binary counter means includes input means comprising count-upinput mean and count-down input means.
 13. The apparatus of claim 12 inwhich the pulse means comprises: pulse generator means having outputmeans; switch means; the switch means connected to the pulse generatoroutput means, the count-up input means and the count-down input means;and the switch means operable to a first position disconnecting thepulse generator output means from the binary counter input means, asecond position connecting the pulse generator output means to thecount-up input means and a third position connecting he pulse generatoroutput means to the count-down input means.
 14. The apparatus of claim13 in which the switch means includes: lever means manually operable toselect each of the first, second and third positions; and meansconnected to the lever means for normally biasing the lever means to thefirst position.
 15. The apparatus of claim 12 in which: the pulsegenerator means includes means for providing pulses at a plurality offrequencies; and said switch means is operable to select any one of thefrequencies when in the second or third position.
 16. In an informationdisplay system in which sets of coordinate points are sequentiallydisplayed on display means, each of the coordinate points having anordinate value and an abscissa value, the improvement comprising:abscissa input means for receiving digital signals representative of theabscissa value of each coordinate point; ordinate input means forreceiving digital signals representaive of the ordinate value of eachcoordinate point; subtraction means having minuend input means,subtrahend input means and difference output means; digital storagemeans having input means and output means; multiplication means havingmultiplicand input means, multiplier input means and product outputmeans; means connecting the abscissa input means to the display means;means connecting the ordinate input means to the minuend input means;means connecting the digital storage means output means to thesubtrahend input means; means connected to the digital storage meansinput means, for selectively supplying digital signals thereto forstorage; means connecting the difference output means to themultiplicand input means; means connected to the multiplier input meansfor selectively supplying signals thereto for varying the multipliervalue; and means connecting the product output means to the displaymeans.
 17. The system of claim 16 in which the means connecting thedigital storage means output means to the subtrahend input meansincludes: inhibit means for selectivley inhibiting transfer ofinformation from the digital storage means to the subtrahend inputmeans.
 18. The system of claim 17 in which the inhibit means includes:gate means connected intermediate the digital storage means output meansand the subtrahend input means; and switch means connected to the gatemeans for selectively enabling the gate means.
 19. The system of claim16 in which: the digital storage means comprises digital up-down countermeans; and the digital storage means input means includes count-up inputmeans and count-down input means.
 20. The system of claim 19 in which:the means for supplying digital signals comprises pulse generator meanshaing output means; and switch means connected intermediate thegenerator output means and the count-up and count-down input means. 21.The system of claim 20 in which: the generator means includes means forgenerating pulses at different rates; and the switch means is movable toconnect a selected rate to the selected one of the count-up andcount-dOwn input means.
 22. The system of claim 16 in which thedifference output means includes: difference limit means for inhibitingtransfer of any number to the multiplier means when the number isgreater than a first predetermined value or less than a secondpredetermined value.
 23. The system of claim 16 in which the productoutput means includes; product limit means for inhibiting transfer ofany number to thedisplay means when the number is greater than a firstpredetermined value or less than a second predetermined value.
 24. Thesystem of claim 16 including: means for entering the ordinate valuecorresponding to the selected abscissa value of any selected coordinatepoint into the digital storage means; and means connecting the means forstoring to the abscissa input means, the ordinate input means and thedigital storage input means.
 25. The system of claim 24 including: markmeans on the display means; and means connecting the means for enteringto the mark means, for marking a selected coordinate point on thedisplay means.
 26. The system of claim 19 including: gated input meanson the up-down counter means; furher counter means having input andoutput means; comparator means having input and output means; meansconnecting the ordinate input means to the gated input means; controlmeans connecting the comparator output means to the gated input means;means connecting the abscissa input means to the comparator input means;means connecting the further counter means output means to thecomparator input means; and means connecting the further counter inputmeans to the means for supplying digital signals.
 27. The system ofclaim 26 including: mark means on the display means for marking aselected displayed coordinate point; and the control means connectedintermediate the mark means and the comparator output means.
 28. Thesystem of claim 27 in combination with the system of claim 20 in which:the further counter means comprises a further up-down counter meanshaving further count-up input means and further count-down input means;and further switch means connected intermediate the generator outputmeans and the further count-up and further count-down input means. 29.The system of claim 28 in combination wih the system of claim 21 inwhich: the furher switch means is movable to connect a selected rate tothe selected one of the further count-up and further count-down inputmeans.
 30. In apparatus for displaying coordinate points on displaymeans, each coordinate point having at least an abscissa value and anordinate value, the improvement comprising: abscissa input means;ordinate input means; means connecting the abscissa input means to thedisplay means; subtraction means for subtracting a selectable value fromeach ordinate value; and means connecting the subtraction means betweenthe ordinate input means and the display means.
 31. The apparatus ofclaim 30 in which the means connecting the subtraction means between theordinate means and the display means comprises: multiplication means formultiplying a received value by a selectable factor.